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description the FT6163 and FT6163l are 73,728-bit ultra high-speed static rams organised as 8k x 9. the cmos memories re- quire no clocks or refreshing and have equal access and cycle times. inputs are fully ttl-compatible. the rams operate from a single 5v10% tolerance power supply. with battery backup, data integrity is maintained for supply voltages down to 2.0v. current drain is 10 a from a 2.0v supply. features full cmos, 6t cell high speed (equal access and cycle times) ? 25/35ns (commercial) ? 25/35/45ns (military) low power operation (commercial/military) output enable and dual chip enable control functions single 5v10% power supply data retention with 2.0v supply, 10 a typical current ()7163l military) common i/o fully ttl compatible inputs and outputs standard pinout (jedec approved) ? 28-pin 300 mil dip, soj ? 28-pin 350 x 550 mil lcc ? 28-pin cerpack functional block diagram pin configurations dip (p5, c5), soj (j5) cerpack (f4) similar access times as fast as 25 nanoseconds are available, per- mitting greatly enhanced system operating speeds. cmos is used to reduce power consumption in both active and standby modes. the FT6163 and FT6163l are available in 28-pin 300 mil dip and soj, 28-pin 350 x 550 mil lcc, and 28-pin cerpack packages providing excellent board level densi- ties. lcc (l5 FT6163/FT6163l ultra high speed 8k x 9 static cmos rams rev 1.2 1/13 2008 a ll data sheet.com
maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +7 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma ambient temperature commercial 0c to +70c 0v 5.0v 10% grade (2) gnd v cc grade (2) gnd v cc ambient temperature military ?55 to +125c 0v 5.0v 10% recommended operating temperature and supply voltage notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. dc electrical characteristics over recommended operating temperature and supply voltage (2) FT6163 FT6163l min max min max v ih input high voltage 2.2 v cc +0.5 2.2 v cc +0.5 v v il input low voltage ?0.5 (3) 0.8 ?0.5 (3) 0.8 v v hc cmos input high voltage v cc ?0.2 v cc +0.5 v cc ?0.2 v cc +0.5 v v lc cmos input low voltage ?0.5 (3) 0.2 ?0.5 (3) 0.2 v v cd input clamp diode voltage v cc = min., i in = ?18 ma ?1.2 ?1.2 v v ol output low voltage i ol = +8 ma, v cc = min. 0.4 0.4 v (ttl load) v olc output low voltage i olc = +100 a, v cc = min. 0.2 0.2 v (cmos load) v oh output high voltage i oh = ?4 ma, v cc = min. 2.4 2.4 v (ttl load) v ohc output high voltage i ohc = ?100 a, v cc = min. v cc ?0.2 v cc ?0.2 v (cmos load) i li input leakage current v cc = max. mil. ?10 +10 ?5 +5 a v in = gnd to v cc com?l. ?5 +5 n/a n/a i lo output leakage current v cc = max., ce = v ih , mil. ?10 +10 ?5 +5 a v out = gnd to v cc com?l. ?5 +5 n/a n/a symbol parameter test conditions unit symbol parameter conditions typ. unit c in input capacitance v in = 0v 5 pf capacitances (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) symbol parameter conditions typ. unit c out output capacitance v out = 0v 7 pf 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. )7)7/ rev 1.2 2/13 2008 a ll data sheet.com
power dissipation characteristics over recommended operating temperature and supply voltage (2) FT6163 FT6163l min max min max i cc dynamic operating v cc = max., f = max., mil. ? 145 ? 145 ma current ? 25 outputs open com?l. ? 125 ? n/a i cc dynamic operating v cc = max., f = max., mil. ? 120 ? 120 ma current ? 35, 45 outputs open com?l. ? 95 ? n/a i sb standby power supply ce 1 v ih or mil. ? 40 ? 40 ma current (ttl input levels) ce 2 v il , v cc = max., com?l. ? 35 ? n/a f = max., outputs open i sb1 standby power supply ce 1 v hc or mil. ? 20 ? 1 ma current ce 2 v lc , v cc = max., com?l. ? 18 ? n/a (cmos input levels) f = 0, outputs open, v in v lc or v in v hc data retention waveform symbol parameter test conditions unit n/a = not applicable data retention characteristics (FT6163l, military temperature only) typ.* max symbol parameter test condition min v cc =v cc =unit 2.0v 3.0v 2.0v 3.0v v dr v cc for data retention 2.0 v i ccdr data retention current 10 15 200 300 a t cdr chip deselect to 0 ns data retention time t r ? operation recovery time t rc ns *t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested. ce 1 v cc ? 0.2v or ce 2 0.2v, v in v cc ? 0.2v or v in 0.2v )7)7/ rev 1.2 3/13 2008 a ll data sheet.com
symbol parameter unit -25 -35 -45 min max min max min max t rc read cycle time 25 35 45 ns t aa address access time 25 35 45 ns t ac chip enable 25 35 45 ns access time t oh output hold from 3 3 3 ns address change t lz chip enable to 3 3 3 ns output in low z t hz chip disable to 10 15 20 ns output in high z t oe output enable 13 18 20 ns low to data valid t olz output enable 3 3 3 ns low to low z t ohz output enable 12 15 20 ns high to high z t pu chip enable to 0 0 0 ns power up time t pd chip disable to 20 20 25 ns power down time ac electrical characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) read cycle no. 1 ( oeoe oeoe oe controlled) (5) notes: 5. we is high for read cycle. 6. ce 1 is low, ce 2 is high and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce 1 transition low and ce 2 transition high. 8. transition is measured 200mv from steady state voltage prior to change, with loading as specified in figure 1. this parameter is sampled and not 100% tested. )7)7/ rev 1.2 4/13 2008 a ll data sheet.com
notes: 9. read cycle time is measured from the last valid address to the first transitioning address. 10. transitions caused by a chip enable control have similar delays irrespective of whether ce 1 or ce 2 causes them. read cycle no. 2 (address controlled) (5,6) read cycle no. 3 ( cece cece ce 1 , ce 2 controlled) (5,7,10) )7)7/ rev 1.2 5/13 2008 a ll data sheet.com
-25 -35 -45 min max min max min max t wc write cycle time 25 35 45 ns t cw chip enable 18 25 33 ns time to end of write t aw address valid to 18 25 33 ns end of write t as address set-up time 0 0 0 ns t wp write pulse width 18 20 25 ns t ah address hold time 0 0 0 ns t dw data valid to end 13 15 20 ns of write t dh data hold time 0 0 0 ns t wz write enable to 10 14 18 ns output in high z t ow output active 3 5 5 ns from end of write ac characteristics?write cycle (v cc = 5v 10%, all temperature ranges) (2) symbol parameter unit write cycle no. 1 ( wewe wewe we controlled) (11) notes: 11. ce 1 and we must be low, and ce 2 high for write cycle. 12. oe is low for this write cycle to show t wz and t ow . 13. if ce 1 goes high, or ce 2 goes low, simultaneously with we high, the output remains in a low impedance state. 14. write cycle time is measured from the last valid address to the first transitioning address. )7)7/ rev 1.2 6/13 2008 a ll data sheet.com
timing waveform of write cycle no. 2 ( cece cece ce controlled) (11) mode cece cece ce 1 ce 2 oeoe oeoe oe wewe wewe we i/o power standby h x x x high z standby standby x l x x high z standby d out disabled l h h h high z active read l h l h d out active write l h x l d in active ac test conditions input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 truth table 1527 10 figure 1. output load figure 2. thevenin equivalent * including scope and test fixture. note: because of the ultra-high speed of the FT6163/l, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance). )7)7/ rev 1.2 7/13 2008 a ll data sheet.com
selection guide the FT6163/l is available in the following temperature, speed and package options. the FT6163l is only available over the military temperature range. * military temperature range with mil-std-883 m5004 n/a = not available ordering information 25 35 45 plastic dip -25pc -35pc n/a plastic soj -25jc -35jc n/a side brazed dip -25cm -35cm -45cm lcc -25lm -35lm -45lm cerpack -25fm -35fm -45fm side brazed dip -25cmb -35cmb -45cmb lcc -25lmb -35lmb -45lmb cerpack -25fmb -35fmb -45fmb military processed* miliitary temperature speed temperature range package commercial m5004 FT6163 FT6163l l xx x x x )7)7/ rev 1.2 8/13 2008 a ll data sheet.com
pkg # # pins symbol min max a 0.120 0.148 a1 0.078 - b 0.014 0.020 c 0.007 0.011 d 0.700 0.730 e e e1 0.292 0.300 e2 q0.025- j5 28 (300 mil) 0.050 bsc 0.267 bsc 0.335 bsc soj small outline ic package pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.342 0.358 d1 d2 d3 - 0.358 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne 0.020 ref 5 9 0.400 bsc 0.200 bsc 0.050 bsc 0.040 ref l5 28 0.200 bsc 0.100 bsc rectangular leadless chip carrier )7)7/ rev 1.2 9/13 2008 a ll data sheet.com
side brazed dual in-line package pkg # # pins symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.485 e 0.240 0.310 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - c5 28 (300 mil) 0.300 bsc 0.100 bsc pkg # # pins symbol min max a 0.060 0.090 b 0.015 0.022 c 0.004 0.009 d - 0.730 e 0.330 0.380 e k 0.005 0.018 l 0.250 0.370 q 0.026 0.045 s - 0.085 s1 0.005 - f4 28 0.050 bsc cerpack ceramic flat package )7)7/ rev 1.2 10/13 2008 a ll data sheet.com
pkg # # pins symbol min max a - 0.210 a1 - b 0.014 0.023 b2 0.045 0.070 c 0.008 0.014 d 1.345 1.400 e1 0.270 0.300 e 0.300 0.380 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p5 28 (300 mil) plastic dual in-line package )7)7/ rev 1.2 11/13 2008 a ll data sheet.com
revisions document number : sram120 document title : ft616/FT6163l ultra high speed 8k x 9 static cmos rams rev. issue date orig. of change description of change orig 1997 m.s new data sheet 1 oct-05 m.s change logo to pyramid 1.1 jul-06 m.s added lead-free designation 1.2 june-08 m.s updated soj package information and data sheet review FT6163/FT6163l rev 1.2 12/13 2008 a ll data sheet.com
ashley crt, henley, marlborough, wilts, sn8 3rh uk tel: +44(0)1264 731200 fax:+44(0)1264 731444 e-mail sales@forcetechnologies.co.uk www.forcetechnologies.co.uk life support applications force technologies products are not designed for use in life support appliances, devices or systems where malfunction of a force technologies product can reasonably be expected to result in a personal injury. force technologies customers using or selling force technologies products for use in such applications do so at their own risk and agree to fully indemnify force technologies for any damages resulting from such improper use or sale. all trademarks acknowledged copyright force technologies ltd 20 unless otherwise stated in this scd/data sheet , force technologies ltd reserve the right to make changes, without notice, in the products, includ -ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. force technologies resumes no responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these products, and makes no representation or warranties that that these products are free f rom patent, copyright or mask work infringement, unless otherwise specified. rev 1.2 13/13 2008 a ll data sheet.com

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